`include "defines.v"

//stall control unit

module scu(

    input              if_ready_i,
    input              mem_ready_i,
    input              mem_valid_i,
    input              id_branch_tag_i,
    input              id_hit_i,

    output wire [4:0]  stall_ena_o,   // [3:0] --> mem,exe,id,if
    output wire [4:0]  pipe_rst_o,
    output wire        mem_req_o
);

    wire if_req, id_req, exe_req, mem_req, wb_req;
    wire if_stall, id_stall, exe_stall, mem_stall, wb_stall;
    wire if_rst, id_rst, exe_rst, mem_rst, wb_rst;

    assign stall_ena_o = {wb_stall,mem_stall,exe_stall,id_stall,if_stall};
    assign pipe_rst_o  = {wb_rst,mem_rst,exe_rst,id_rst,if_rst};
    assign mem_req_o   = mem_req;

    //stall_req
    assign if_req    = ~if_ready_i;
    assign id_req    = id_branch_tag_i & id_hit_i;
    assign exe_req   = 0;
    assign mem_req   = ~mem_ready_i & mem_valid_i;
    assign wb_req    = 0;
    //stall
    assign if_stall  = id_req  | exe_req | mem_req;
    assign id_stall  = exe_req | mem_req;
    assign exe_stall = mem_req;
    assign mem_stall = 0;
    assign wb_stall  = 0;
    //rst
    assign if_rst    = if_req;
    assign id_rst    = id_req;
    assign exe_rst   = exe_req;
    assign mem_rst   = mem_req;
    assign wb_rst    = wb_req;



endmodule
